Programmable array logic circuit macrocell using ferromagnetic memory cells

ABSTRACT

A programmable array logic circuit macrocell using ferromagnetic memory cells. More particularly, the present invention uses a non-volatile ferromagnetic memory cell to temporarily store binary data. It is an advantage of the invention to have the ferromagnetic memory cells or bits to store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shutdown. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein, thus eliminating “write fatigue”. The invention provides an integrated circuit, comprising a programmable OR array ( 24 ), a programmable AND array ( 28 ), coupled to the programmable OR array, and a macrocell output circuit ( 22 ). The macrocell uniquely has a ferromagnetic bit ( 11 ) and sensor ( 12 ) coupled to store remnant output signal, and an output buffer ( 34 ), coupled to output the remnant output signal upon receiving an output enable signal. The macrocell may further include a DQ register that contains the ferromagnetic bit. The DQ register may also include a drive coil, which at least partially surrounds the ferromagnetic bit. Drive coils may have a bi-directional current that sets the polarity of the ferromagnetic bit. The bi-directional current may be switched by two sets of transistor pairs (Q 10  and Q 11 ). The two sets of transistor pairs may, in turn, be gated by first and second transistor respectively. The first and second transistors may be responsive to a DATA signal that is received when a CLOCK signal is received.

This application is a 371 of application Ser. No. PCT/US01/01790 filedJan. 20, 2001, which claims benefit of 60/177,478 filed Jan. 21, 2000.

BACKGROUND OF THE INVENTION

1. The Field of the Invention

The present invention relates generally to a programmable array logiccircuit macrocell using ferromagnetic memory cells. More particularly,the present invention uses a non-volatile ferromagnetic memory cell totemporarily store binary data.

2. The Background Art

Programmable logic devices have any number product sets, usually ingroups of four (4), eight (8), sixteen (16) or more bits, although oftenin groups of ten (10). The arrays are programmed forapplication-specific tasks to be performed within digital electroniccircuits. The fusible link types cannot be re-programmed, but thoseemploying EEPROM and Flash can. For those PALs which use fusible links,the data in the “D” registers is lost at power off. For those that useEEPROM and Flash as replacements for the “D” registers, data is not lostat power off time.

Up to the present, traditional PALs have used “D” type flip-flops forproduct registers. Lately, however, some fabricators have begun usingEEPROM and Flash technology to replace these. These last twotechnologies have drawbacks, however. EEPROMs are cumbersome tore-program, both are slow to re-program, exhibit “write fatigue,”thereby limiting their useful life, and must be mass-written tore-program.

SUMMARY OF THE INVENTION

It has been recognized that it would be advantageous to develop aprogrammable array logic circuit macrocell using ferromagnetic memorycells. More particularly, the present invention uses a non-volatileferromagnetic memory cell to temporarily store binary data.

It is an advantage of the invention to have the ferromagnetic memorycells or bits to store data even when there is no power provided to thecircuitry, thus saving power during operation of the programmable logiccircuitry, and ensuring that there is no loss of the data should therebe a temporary power shut down.

Additionally, the ferromagnetic cells provide for indefinite number ofswitching actions on the data without degradation to the capacity tostore data therein, thus eliminating “write fatigue”.

The invention provides an integrated circuit, comprising a programmableOR array, a programmable AND array, coupled to the programmable ORarray, and a macrocell output circuit. The macrocell uniquely has aferromagnetic bit and sensor coupled to store a remnant output signal,and an output buffer, coupled to output the remnant output signal uponreceiving a output enable signal. The macrocell may further include a DQregister that contains the ferromagnetic bit. The DQ register may alsoinclude a drive coil, which at least partially surrounds theferromagnetic bit. Drive coils may have a bi-directional current thatsets the polarity of the ferromagnetic bit. The bi-directional currentmay be switched by two sets of transistor pairs. The two sets oftransistor pairs may, in turn, be gated by first and second transistorrespectively. The first and second transistors may be responsive to aDATA signal that is received when a CLOCK signal is received.

Additional features and advantages of the invention will be set forth inthe detailed description which follows, taken in conjunction with theaccompanying drawing, which together illustrate by way of example, thefeatures of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic of a preferred embodiment of the presentinvention.

FIG. 2 is a schematic of a preferred embodiment of the presentinvention.

FIG. 3 is a cross sectional view of a single ferromagnetic memory bit.

FIG. 4 is a schematic of a field programmable logic device capable ofutilizing the present invention.

DETAILED DESCRIPTION

For the purposes of promoting an understanding of the principles of theinvention, reference will now be made to the exemplary embodimentsillustrated in the drawings, and specific language will be used todescribe the same. It will nevertheless be understood that no limitationof the scope of the invention is thereby intended. Any alterations andfurther modifications of the inventive features illustrated herein, andany additional applications of the principles of the invention asillustrated herein, which would occur to one skilled in the relevant artand having possession of this disclosure, are to be considered withinthe scope of the invention.

For the purpose of providing background material which may in somerespects illustrate the state of the are, the following books are hereinincorporated by reference for non-essential material: “ProgrammableLogic Handbook,” fourth edition, by Monolithic Memories Inc., 2175Mission College Blvd., Santa Clara, Calif.; and “Practical Design UsingProgrammable Logic,” by D. Pellerin and M. Holley, Prentice Hall,library of Congress no. TK7872.L64 1991.

The following United States patents are herein incorporated by referencefor their supporting teachings:

U.S. Pat. No. 5,300,830, is a programmable logic device macrocell withan exclusive feedback and exclusive external input lines for registeredand combinatorial modes using a dedicated product term for control.

U.S. Pat. No. 5,287,017, is a programmable logic device macrocell withtwo OR array inputs.

U.S. Pat. No. 5,324,998, is a zero power re-programmable flash cell fora programmable logic device.

U.S. Pat. No. 5,295,097, is a nonvolatile random access memory.

U.S. Pat. No. 5,867,049, is a zero setup time flip flop.

U.S. Pat. No. 5,298,803, is a programmable logic device having low powermicrocells with selectable registered and combinatorial output signals.

The invention is used in the normal arena in which PALs are employed,but where it may be advantageous to retain the last data stored afterremoval of power to the circuit as well as the simplicity of randomre-programming. This PAL circuit could be in all manner of digitalcircuitry, including computers, robotics, telephones, automotivecircuits, security devices, and so on. The advantages over prior art lieprincipally in that PAL devices using ferromagnetic digital memory cellsfor product registers would enjoy non-volatility, high-speed in siturandom re-programmability and indefinite long life span.

A PAL having product registers (flip flops) that use non-volatileferromagnetic memory/storage cells for product storage registers isdescribed wherein the non-volatile ferromagnetic memory cells, comprisedof single stick-like ferromagnets whose aspect ratio is greater than 1:1(height to width, e.g. 2:1 etc.), are fabricated normal to the plane ofthe substrate with a sensor centered intimate to, and at one end of theferromagnets are used for these functions. The magnetic polarity of eachferromagnetic memory cell bit is coerced into reversal using write, orstate change circuitry, comprised of a coil which surrounds, up to andincluding 270°, and is intimate to, the ferromagnetic stick. The writecurrent in each coil is bi-directional, depending on the desiredmagnetic movement, or polarity, of the bit. The output of the sensorreflects the binary condition of the bit, and is used as binary dataoutput for product registers.

FIG. 1 is a schematic of a dual output storage register 10, orflip-flop, which is comprised of a ferromagnetic memory cell consistingof micron or sub-micron sized ferromagnetic bit whose aspect ratio isgreater than 1:1 (i.e., 2:1, etc.), deposited normal to the plane of thesubstrate with its attendant support circuitry. Uniquely, there is aferromagnetic stick (bit) 1, which is at least partially, but notnecessarily completely, surrounded by a write drive coil 2. Thebi-directional current in the write drive coil sets the polarity of thebit and is switched by two sets of transistor pairs, or switches. Thefirst transistor pair being Q3 and Q6, having reference number 4 a, andthe second pair being Q4 and Q5, having reference number 4 b. Theseswitches are in turn gated by Q1 and Q2, having reference number 7. Witha signal on the DATA 21 line and a positive-going pulse on the CLOCK 20line, either Q7 or Q8 will be activated to allow the memory cell 1 to beset to one binary position or another. Other features of the drawingare: capacitor C1, diode D1, resistors R3 tied to ground, and R4 and R5which are both tied to power+.

On a second portion of the flip-flop 10, or storage register circuit,there is a ferromagnetic bit field sensor 3, which is capable of sensingremnant polarity stored in the bit 1. It is noted that the dashed lineis meant to illustrate the fact that the sensor 3 is to be physicallylocated proximate the top or bottom of the ferromagnetic bit 1, but isillustrated at a spaced relationship for schematic purposes only and notmeant to illustrate physical layout as is shown in FIG. 3. Additionally,amplifiers U1 and U2, having reference number 5, respond based on theHall voltage that appears across the sensor 3. The outputs are fed tothe transistors Q10 and Q11, reference number 6, whose outputs, in turn,are “Q” and “Q*”. In summary, the DATA is set into the cell with therising CLOCK line and stored in the ferromagnetic memory bit 1 despiteany power shutdown after being stored. Thereafter, the output in thiscase employs two operational amplifiers whose differential outputs arefed; one to the Q output and the other, Q* to the product feedbackcircuit.

Since the ferromagnetic bit does not change state when power to thecircuit is off, when power has thereafter been restored subsequent to apower off, the storage registers will have retained their critical data.Additionally, even while there is power to the programmable logicdevice, it is noted that additional power is not required to maintainthe stored state in the flip-flop 10, thus, saving overall powerconsumption.

FIG. 2 is a representation of the “DQ” type register or flip-flop 10 ofFIG. 1 and is part of the output macrocell circuitry 22 that receivesdata from an OR array 24 from a typical PAL 30, (programmable arraylogic). It is noted that one skilled in the art will easily realize thatthe bit 1 will store a remnant polarity in the ferromagnetic materialthat the sensor 3 will be able to sense. Thus, creating a remnant outputsignal that will cause the amplifiers 5 to simultaneously and constantlyopen or close the gates of output transistors 6 accordingly; and wherethe polarity of the bit will exist even after the power to the circuitryhas been turned off. To output the data signal Q, output enable signalline 32 will pulse to enable the output amplifier 34, or output buffer.

FIG. 3 depicts, for example, a potential cross-section of a micron orsub-micron scale ferromagnetic memory cell with the sensor shown on thebottom. There is a ferromagnetic storage element 11, or “bit,” a sensor12, a sample drive line 14, which is made of Al, Cu or any othersuitable conductor material. Additionally there is a cutaway of the set(write) drive coil 13 that wraps around bit 11. In this depiction,matrix interconnects are not shown for the sake of clarity. The entirememory cell rests on substrate 19, which can be silicon, glass, GaAs, orother suitable material. Insulation layer 15 resides between theferromagnetic bit 11 and the set coil 13. Material layer 15 can be of amaterial such as SiO₂ or Si₃N₄, etc. There is an overall insulationsections 16, 17 and 18, again made of SiO₂, Si₃N₄, or other suitablematerial.

Several methods may be employed to make this cell, including, but notlimited to, electroplating, sputtering, E-beam deposition, chemicalvapor deposition and molecular beam epitaxy.

Referring to FIG. 4, there is an embodiment of the invention beingutilized in a field programmable logic device 30. One skilled in the artwill recognize that there is a programmable AND 28 array with inputs andoutputs. Similarly, there are two programmable OR arrays 24 and 26 thatrout signals through various levels or numbers of logical OR gatesbefore the sum of products are sent to designated macrocells.Additionally, there is illustrated macrocell 22. It is noted that themacrocells have one of the flip-flops 10 located therein.

It is understood that the above-described arrangements are onlyillustrative of the application of the principles of the presentinvention. Numerous modifications and alternative arrangements may bedevised by those skilled in the art without departing from the spiritand scope of the present invention and the appended claims are intendedto cover such modifications and arrangements. Thus, while the presentinvention has been shown in the drawings and fully described above withparticularity and detail in connection with what is presently deemed tobe the most practical and preferred embodiment(s) of the invention, itwill be apparent to those of ordinary skill in the art that numerousmodifications, including, but not limited to, variations in size,materials, shape, form, function and manner of operation, assembly anduse may be made, without departing from the principles and concepts ofthe invention as set forth in the claims.

What is claimed is:
 1. An integrated circuit, comprising: a) aprogrammable OR array; b) a programmable AND array, coupled to theprogrammable OR array; and c) a macrocell output circuit, having: 1) aferromagnetic bit and sensor coupled to store a remnant output signal;and 2) an output buffer, coupled to output the remnant output signalupon receiving an output enable signal.
 2. The integrated circuit ofclaim 1, wherein the macrocell further includes a DQ register thatcontains the ferromagnetic bit.
 3. The integrated circuit of claim 2,wherein the DQ register includes a drive coil, which at least partiallysurrounds the ferromagnetic bit.
 4. The integrated circuit of claim 3,wherein drive coil has a bi-directional current that sets the polarityof the ferromagnetic bit.
 5. The integrated circuit of claim 4, whereinthe bi-directional current is switched by two sets of transistor pairs.6. The integrated circuit of claim 4, wherein the two sets of transistorpairs are in turn gated by a first and a second transistor respectively.7. The integrated circuit of claim 4, wherein the first and secondtransistors are responsive to a DATA signal that is received when aCLOCK signal is received.
 8. An integrated circuit, comprising: a) aprogrammable logic array; and b) a macrocell output circuit, coupled tothe programmable logic circuit, having: 1) a ferromagnetic bit andsensor coupled to store a remnant output signal; and 2) an outputbuffer, coupled to output the remnant output signal upon receiving anoutput enable signal.
 9. The integrated circuit of claim 8, wherein theprogrammable logic array includes a logical AND array and a logical ORarray.
 10. The integrated circuit of claim 8, wherein the ferromagneticbit has a height that is greater than its width.
 11. The integratedcircuit of claim 10, wherein the macrocell output circuit has asupporting substrate, to support the ferromagnetic bit to have theheight oriented perpendicular thereto.
 12. The integrated circuit ofclaim 11, wherein the sensor is located below the ferromagnetic bit andabove the substrate.
 13. The integrated circuit of claim 12, wherein themacrocell output circuit has a set and reset input to program theremnant output signal that is to be stored in the ferromagnetic bit. 14.A programmable logic device, comprising: a) a programmable logic array;and b) a macrocell output circuit, coupled to receive resultant signalsprocessed through the programmable logic array, having: i) aferromagnetic bit coupled to store a remnant output signal; and ii) anoutput buffer, coupled to output the remnant output signal uponreceiving an output enable signal.
 15. The programmable logic device ofclaim 14, wherein the programmable logic array includes a programmableOR array.
 16. The programmable logic device of claim 14, wherein theprogrammable logic array includes a programmable AND array.
 17. Theprogrammable logic device of claim 16, wherein the macrocell outputcircuit further includes a sensor, positioned proximate to theferromagnetic bit, to sense the polarity of the ferromagnetic bit and tocreate the remnant output signal therefrom.
 18. The programmable logicdevice of claim 17, wherein the ferromagnetic bit has a height that isgreater than its width.
 19. The programmable logic device of claim 18,wherein the macrocell output circuit has a supporting substrate, tosupport the ferromagnetic bit to have the height oriented perpendicularthereto.
 20. The programmable logic device of claim 19, wherein thesensor is located below the ferromagnetic bit and above the substrate.21. The programmable logic device of claim 20, wherein the macrocelloutput circuit has a set and reset input to program the remnant outputsignal that is to be stored in the ferromagnetic bit.